Evolution of Logic Analyzers: Future of Logic Analyzer in embedded system design
Traditionally Logic Analyzers are used to monitor parallel bus in microprocessor, micro controllers or PATA or memory interfaces based designs. Data transfer between microprocessor and peripherals ICs is using parallel bus. Programming of microprocessor or microcontroller used to be in assembly language. In order to support debug digital design Logic Analyzers provided 100s of channels, advanced parallel pattern triggers, long acquisition memory and disassemblers for different microprocessor and microcontrollers. Disassembler is additional hardware commonly called ‘PODS’ used to capture the data in microprocessor/microcontrollers IOs. Software associated with the POD used disassembly the captured data and display it in assembly language. This runtime assembly language code used to provide great details enabling designers to debug and optimize the designs.
But modern electronics designs moved away from parallel bus design for good and adapted serial bus architecture for low speed, high and ultra-high speed designs. Current digital designs are based on system on chip which has multiple low speed and sigh speed serial bus interfaces to support different design needs. Data transfer between ICs or peripherals takes places using protocol using the serial bus. Product differentiation is driven by software features which continuously updated to add more capabilities. This has driven demand for different set of capabilities in Logic Analyzer. In order to support these design needs Logic Analyzer no need to be high channel count but it should be capable of capturing data from multiple serial bus design and display it time correlated form so that designers can visualize the system level operation. But just viewing the digital waveforms it is extremely difficult to interpret the serial data. Hence Logic Analyzer should provide multiple serial bus decoding capabilities. This simplifies entire debug process.
Debugging any design is very challenging activity. Designers need find the root cause using the symptoms such as bus failure, boot failure etc. Designers try to narrow down by eliminating different possible causes to the symptoms by looking at specific data and analyzing them. In order to get to the specific cause, Logic analyzer should have capability to define trigger on specific event or ability to look for multiple events and take smart actions so that root cause to the systems can be found.
This New generation Logic Analyzer to support following capabilities.
- Good enough number of channel count (could be 10 to 32)
- Serial bus data analysis for different Protocols
- Simultaneously decode multiple Protocols
- Protocol aware trigger capabilities
- Long acquisition support with pre and post trigger capabilities