PGY-LA-EMBD is an industry-first logic analyzer in its category which enables engineers to debug timing problems and perform simultaneous protocol analysis of I2C, SPI, UART or I3C, SPMI, and RFFE in embedded designs. This enables designers to debug circuit-level and system-level problems quickly.
PGY-LA-EMBD offers 1GS/Sec asynchronous (timing) data and 100Mhz synchronous (state) data capture which makes it an ideal debug tool to address the digital design problems. Designers can now easily analyze setup and hold time issues, glitches, and synchronous data activities apart from analyzing protocol issues.
Current generation embedded designers need to collect data from multiple interfaces such as I2C, SPI, UART, I3C, SPMI, and RFFE and process it to achieve optimal performance of their designs. Embedded design teams need to take timely action to meet the intended objectives of the product. PGY-LA-EMBD simultaneously decodes I2C, SPI, UART, I3C, SPMI, and RFFE bus and displays the protocol activity with timestamp information. PGY-LA-EMBD is an ideal instrument to debug the hardware and embedded software integration issues and optimize the software performance.
Multiple markers enable smart delta measurements which are key to designers. Zoom enables users to look at specific areas of the signal.
- 16 channels with Protocol and Logic Analysis capability.
- 1GS/Sec Timing (Asynchronous) Analysis
- 100MHz State (Synchronous) Analysis
- Simultaneous Protocol Analysis of I2C- SPI-UART-I3C-SPMI and RFFE.
- Detailed Trigger capabilities: Auto, Pattern, Protocol awareness (I2C, SPI, UART, I3C, SPMI, RFFE), and Timing (Pulse Width and Delay Trigger).
- Smart streaming of data from Protocol. Analyzer to host computer for long duration capture using USB3 interface.
- Innovative easy-to-use Graphic user interface.
- Error Analysis of Protocol packet
- Provides timing, waveform, listing, and Protocol listing views
- Detailed filtering capability for protocol decoded data
- PDF and CSV report format.
- API support.