I2C Signal Integrity: Measurement and Electrical Validation
Overview of I2C Bus:
The I2C’s physical two-wire interface consists of a bi-directional serial clock (SCL) and data (SDA) lines. Each device that is connected to the bus is software-addressable by a unique address and a simple master/slave relationship with the bus exists all the time. I2C is a serial, 8-bit oriented, bi-directional data transfer that can be made at 100Kbits/s in the standard mode, up to 400Kbits/s in the Fast mode, up to 1Mbits/s in fast Mode plus, or up to 3.4Mbits/s in the high-speed mode. On-chip filtering rejects spikes on the bus data line to preserve data integrity.
Phillips Semiconductor (now NXP Semiconductors) has published I2c electrical specifications and I2c protocol specifications since 1982. The recent I2C bus specification and user manual were published in the year 2007. By following the electrical and protocol specification in the I2C document, semiconductor design, and manufacturing companies can ensure the interoperability of ICs using the I2C Bus.
I2C protocol overview:
Typical data transfer between two ICs using the I2C interface is as shown:
All transactions start with START Condition and stop with STOP condition In I2C Bus. These two conditions are controlled by the master IC. The typical I2C frame format has the following contents: START, address, read/write, data followed by ACK/NACK, and STOP condition at the end of the operation.
START: A condition where high to low transition of SDA line occurs when SCL is held high. The is initiated by the master IC.
Address: Master sends the slave the 7-bit or 10-bit address of the slave device
Read/write: The slave address is followed by this bit. A ZERO indicates a transmission (write), and a ‘ONE’ indicates a request for READ.
Acknowledge (ACK) and Not Acknowledge (NACK): This takes place after every byte. During this condition, the transmitter releases the SDA line during the acknowledged clock pulse so that the receiver can pull the SDA line LOW, and the SDA line remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during this 9th clock pulse, this is defined as the Not Acknowledgement signal. The master can then regenerate either a STOP condition to abort the transfer or a repeated START condition to start a new transfer.
Data is an integer number of bytes read or written into a device.
STOP: A condition during SDA transitions from LOW to HIGH when SCL is held high indicating the end of a transfer of data.
I2C Bus Electrical Measurements:
For successful interoperation of IC using an I2C bus, the electrical characteristics of physical layer signals of I2C SCL and SDA signals should be compatible. The timing between the master and slave devices should be within the electrical specifications defined in the I2C Specification by NXP Semiconductor. The electrical measurement list is as follows:
| Symbol | Parameter | Symbol | Paramater |
| fSCL | SCL Clock Frequency | tr | rise time of both SDA and SCL Signals |
| tHD;STA | hold time (repeated) START condition | tf | fall time of both SDA and SCL signals |
| tLOW | Low Period of the SCL clock | tSU; STO | set-up time for STOP condition |
| tHIGH | High Period of the SCL clock | tBUF | bus free time between a STOP and START
condition |
| tSU;STA | set-up time for a repeated START
condition |
tVD; DAT | data valid time |
| tHD;DAT | Data hold time | tVD; ACK | data valid acknowledge time |
| tSU;DAT | Data setup time |
The detailed definitions of each of these measurements are as below:
fSCL SCL Clock frequency: Inverse of one cycle period measured at 30% of the amplitude of SCL signal. It should be measured at the first cycle after the START condition.
tr, rise time of the SCL and SDA signals: time is taken by the rising edge to reach 70% of the amplitude from 30% of the amplitude of SCL and SDA signals.
tf fall time of the SCL and SDA signals: time is taken by the falling edge of the signals to reach 30% of the amplitude from 70% of the amplitude of SCL and SDA signals
tHD;STA hold time (repeated) START condition: Minimum time the data should be low before SCL is in a low state at (repeated) START condition. It is measured as the time taken from 30% of the amplitude of SDA at high to low transition to 70% of the amplitude at high to low transition of SCL Signal.
tLOW Low period of the SCL signal: It is the minimum low time that should be maintained by the SCL signal. It is measured as half period measured at 30% of the amplitude of the SCL signal.
tHIGH High period of the SCL Signal: It is the minimum high time that should be maintained by the SCL signal. It is measured as a half period measured at 70% of the amplitude of the SCL signal.
tSU; STO Setup time at STOP condition: It is measured at STOP condition of the I2C frame. It is measured as the time between 70% of the amplitude at the rising edge of the SCL signal to 30% of the amplitude of the SDA signal at the STOP condition.
tSU;STA Setup time for repeated START condition: This measurement is carried out at repeated START conditions only. It is time measured between SCL and SDA signals at 70% amplitude of the signals.
tVD; DAT Data Valid time: Measured at every data and clock transition. This is measured concerning the 30% amplitude falling edge of SCL to 70% of the rising edge or 30% of the falling edge of the SDA signal. The I2C specification maximum allowed data valid time at different I2C speeds.
tVD; ACK data valid acknowledge time: Measured at acknowledgment bit. It is the time from 30% of the falling edge of the eighth clock from the start of data to 70% of the ack bit or 30% of the ack bit.
I2C Protocol Electrical Measurement Challenges:
During the electrical validation of the I2C bus, test engineers need to ensure the I2C bus should comply with the electrical parameters of the I2C Bus. The challenges faced while the electrical validation of the I2C bus is as follows:
- Test/Design Engineer must know I2C Protocol behavior at the physical layer of I2C Bus
- Electrical parameter measurements must be carried out at different protocol states (for example; stop bit, ack bit, and so forth)
- Reference level for each of the measurement changes based on the rising or falling edge of the I2C signal transition
- The reference level is either 30% or 70% as against the normally used reference level of 10% to 90% or 20% to 80%
- Validation is time-consuming
Overall, measuring I2C electrical measurements demands a very high level of expertise in I2C physical layer behavior, protocol layer, signal acquisition in an oscilloscope, and I2C Electrical measurement procedures. Due to the complexity of I2C Electrical measurements, the results can be prone to errors.
The Solution to I2C Bus Electrical Measurements:
Prodigy offers I2C Electrical Validation and Protocol Decode Software to measure I2C setup and hold time, and I2C rise time. PGY-I2C Electrical Validation and Protocol Decode software offers PHY layer measurements for checking the I2C signal integrity issues.
The PGY-I2C Electrical Validation and Protocol Decode Software offer electrical measurements and protocol decoding as specified in Rev 03, June 2007 I2C Bus specification. Now design and test engineers can automatically make accurate and reliable electrical measurements and decode protocols in PGY-I2C software using data acquired by Tektronix DPO5000, DPO7000, DPO/DSA/MSO70000 Series oscilloscope to reduce the development and test cycle.
PGY-I2C Software runs inside Tektronix oscilloscopes. During the run operation of the application, PGY-I2C sends commands to acquire SCL and SDA signals of the I2C bus. For accurate measurements, the recommended oscilloscope setup is:
- The signal is at least 5 to 6 six main vertical divisions in the oscilloscope display with the appropriate volts per division.
- Select the appropriate volts per division to display the signal with at least 5 or 6 main vertical divisions.
- Select a sample rate such that at least 8 to 10 samples are present in the rising or falling edge of SCL and SDA signals.
- Set record length such that at least two I2C frames are captured to make the most of I2C signals.
The PGY-I2C software analyzes the acquired data for the I2C protocol. The selected measurements are displayed as follows:
Electrical Measurement results with limits as specified in I2C standard document
The application makes each of the I2C electrical measurements in every possible I2C protocol state and displays the min, max, and mean values. If the mean value is within the limit specified, the application shows ‘Pass’. But in case, if the mean value is a pass but either the min or max values exceed the limits, applications show‘ pass*’ with an asterisk.
PGY-I2C makes all these measurements in an instant of time addressing all the challenges of I2C electrical measurements, giving accurate and reliable measurements.
Summary:
PGY-I2C Electrical Validation and Protocol Decode software offer the industry’s best I2C Electrical Validation and protocol decode software. This software allows design and test engineers to characterize the I2C bus for compliance with I2C bus standard specifications.
PGY-I2C software has the leading feature ‘Detail View’ to debug the I2C bus at the physical layer and at the protocol layer for electronic system-level development.
PGY-I2C software runs inside industry-leading Tektronix oscilloscopes such as DPO5000, DPO7000, and DPO/MSO/DSA70000 to offer the most accurate and reliable solution.
Prodigy also provides I2C Protocol Analyzer and Exerciser with multiple features to capture and debug communication between host and design under test. Prodigy’s I2C/SPI Protocol Analyzer and Exerciser is the leading instrument that enables the design and test engineers to test the respective I2C or SPI designs for their specifications by configuring the PGY-I2C/SPI-EX-PD as Master/Slave, generating I2C/SPI traffic and decoding the I2C/SPI protocol decode packets.
