UFS 4.0 Protocol Analyzer
Product
Overview
Datasheet
Presentation
Application
Notes
PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.
PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.
XSPI Protocol Analyzer
Key features
- Provides industry best probing solutions to simultaneously capture commands, response and data in 1S-1S-1S and 8S-8S-8S mode.
- Data capture at 250MHz
- Continuous streaming of protocol data to host system SSD/HDD for long duration
- Hardware based protocol aware trigger capability enables capturing specific events
- On the fly protocol validation for any failure in sequence of expected commands and response
- Analytical information about commands, response, and data
- Analytics provides the decoding of device registers for easy analysis
- Filter feature allows you to view specific packets in decoded protocol packets
- Search for specific events in protocol activity
- Easy to use software user interfaces reduces the learning curve of protocol analysis
- Software is designed to handle long duration capture and display the decoded data without demanding extensive resources in host computer
- Trigger out signal for any specific protocol event allows triggering of other instruments such as oscilloscope
- Interface to host system using USB3.0 interface
- Flexibility to upgrade the hardware firmware provides easy field up gradation of firmware
- Decoded data packets can be exported to txt file for further analysis
- Upgradable to support QSPI, eMMC, SD and SDIO Protocol Analysis
- Report Generation
PGY-STG-PA XSPI Protocol Analyzer is the most feature rich comprehensive Protocol validation product available to validate, analyze and debug XSPI/OSPI Protocol layer. PGY-STG- -PA XSPI Protocol Analyzer supports XSPI Protocol analysis for wide data rate up to 250MHz DDR mode. The innovative active probe has minimum electrical loading on device under test (DUT) and allows the protocol data capture without affecting the performance DUT. PGY-STG-PA Protocol analyzer allows industry first continuous streaming of protocol data to host system.
PGY-STG-PA XSPI Protocol Analyzer allows Design and Test Engineers to test and debug XSPI interface by capturing the XSPI protocol activity from power on state and full transfer while the device under test switching from one lane to eight lane mode and analyzes the protocol errors. This helps the design and test engineer debug design issues and reducing the time to market.
Key Specifications
Specifications
Interfaces Supported | XSPI andOSPI |
Protocol Decode | Command,Response,CRC,Data,Arguments, Device registers |
Data Decode | 1 bit, 8 bit |
Timing Analysis | Asynchronous high speed data capture to analyze the timing issues |
Operating Voltage levels | 1.2V, 1.8V and 3.3V |
Storage Capability | Continuous streaming of acquired protocol to host computer storage system |
Simultaneous monitoring of devices | Two |
Capture Mode | Manual Run/Stop, Time specific |
Trigger on | Command,Response, If-then-else multileveltrigger capabilities |
Trigger Actions | Capturedata and/ortrigger out signal |
Signal Input | Digital Signal input to mark the activities in Protocol activity |
Host System Interface | USB3.0 |
