SMBus Protocol Exerciser and Analyzer

PGY-SMBus-EX-PD is the leading SMBus Protocol exerciser and analyzer that enables the design and test engineers to test their SMBus designs against SMBus specifications by configuring PGY-SMBus-EX-PD as master/slave, generating SMBus traffic with error injection capability and decoding SMBus Protocol packets.

Features
The product features are as follows:

• ​Supports SMBus protocol (version 3.2) and speeds up to 3.4 Mbps.
• Configure it as Master or Slave. Can work Standalone with internal Master and Slaves (up to 3).
• Supports all SMBus protocols like Quick Command, Send Byte, Receive Byte, Write Byte / Word, Read Byte/Word, Write 32, Read 32, Write 64, Read 64, Block Write, Block Read, Process Call, Host notify, etc.
• Support for Address Resolution Protocol (ARP)
• Ability to generate and receive packets with (or) without PEC (Packet Error Checking) byte.
• Supports Clock stretching at the slave end.
• Simultaneously generate SMBus traffic and Protocol decode of the Bus.
• Ability to configure the bus voltage level from 1V to 3.3V insteps of 50mV.
• Can define parameters like setup time before repeat start, stop, clock after start, clock in to data out, etc.
• Support script to execute the same set of commands multiple times (Loop Feature)
• Continuous streaming of protocol data to the host computer to provide a large buffer.
• Timing diagram of Protocol decoded bus.
• Error Analysis in Protocol Decode
•  USB 2.0/3.0 host computer interface.
• ​​API support for automation in Python or C++.

Multi-Domain view

Figure 1: Snapshot of PGY-SMBus-EX-PA (SMBus Protocol Exerciser & Analyzer software)

Multi-Domain View as in Figure 1 provides the complete view of SMBus Protocol activity in a single GUI. Users can easily set up the analyzer to generate SMBus traffic using the GUI or script. Users can set different trigger conditions from the setup menu to capture Protocol activity at specific events and decode the transition between Master and Slave. The decoded results can be viewed in the timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the SMBus protocol activity.

Exerciser

Figure 2: Configure as Internal Master

 

Figure 3: Configure ARP-capable slave with dynamic address assignment of 60h

 

Figure 4: Sample SMBus Script

 

PGY-SMBus-EX-PD supports SMBus traffic generation using GUI and Script. Users can generate simple SMBus using the GUI to test the DUT (Device Under Test). Script-based GUI provides flexibility to emulate the complete expected traffic in the real world including error injections. The script in Figure 4 generates SMBus traffic with the Write 32 command. The comments are included in the script.

Timing Diagram and Protocol Listing View

Figure 5: Timing Diagram and Protocol Listing View

The timing view provides the plot of SCL and SDA signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors.

Figure 6: Decoded result window and details of the Selected Frame

The protocol window provides the decoded packet information in each state and all packet details with error info in a packet. The selected frame in the Protocol listing window will be autocorrelated in the timing view to view the timing information of the packet.

Powerful Trigger Capabilities

Figure 7: Trigger Setup view

PGY-SMBus-EX-PD supports Auto, simple, and advanced trigger capabilities. The analyzer can trigger on any of the SMBus Protocol packets. Advanced Trigger provides the flexibility to monitor Multiple trigger conditions and can set multiple state trigger machines.

SMBus Protocol Exerciser & Analyzer Specifications