UFS 4.0 Protocol Analyzer
Product
Overview
Datasheet
Presentation
Application
Notes
PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.
PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.
QSPI Protocol Exerciser and Analyzer Datasheet
Key features
- Supports QSPI speeds of up to 80MHz*
- Ability to configure it as Master or Slave
- Simultaneously generate QSPI traffic and Protocol decode of the Bus
- QSPI Master and Slaves
- STR and DTR Transfer rates
- Extended, Dual, and Quad QSPI Modes Supported
- Variable QSPI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer in sniffer mode
- The timing diagram of the protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Multi-Domain view
Multi-domain View provides the complete view of QSPI Protocol activity in a single GUI. Users can easily set up the analyzer to generate QSPI traffic using a GUI or script. Users can capture Protocol activity at specific events and decode the transition between Master and Slave. The decoded results can be viewed in the timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the QSPI protocol activity.
Exerciser
PGY-QSPI-EX-PD supports QSPI traffic generation using GUI and Script. Users can generate simple traffic generation using the GUI to test the DUT. Script-based GUI provides flexibility to emulate the complete expected traffic in the real-world including error injections. In this sample script user can generate QSPI traffic as below:
Script Line #1: PAGE_PROGRAM
Script Line #2: FAST_READ
Script Line #3: PAGE_PROGRAM
Script Line #4: FAST_READ
Script Line #5: SECTOR_ERASE
Script Line #6: FAST_READ
Timing Diagram and Protocol Listing View
The timing view provides the plot of CS, CLK, DQO, and DQ1 signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors.
The protocol window provides the decoded packet information in each state and all packet details with error info in the packet. The selected frame in the Protocol listing window will be autocorrelated in the timing view to view the timing information of the packet.
Setup View
Setup View of PGY-QSPI-EX-PD allows the user to configure the QSPI chip select (CS), Clock Polarity (CPOL), Clock Phase (CHPA), QSPI rate of STR or DTR, and the different modes of QSPI such as Extended, Dual or Quad.
QSPI Specifications
Appendix 1
The PGY-QSPI-EX-PD unit will work for Frequencies up to 80MHz only in the below-mentioned configurations. This is also subject to the fact that the QSPI Exerciser and Protocol analyzer is connected to the DUT using a board- to board connection.
Key Specifications
