UFS 4.0 Protocol Analyzer

Product
Overview

Datasheet

Presentation

Application
Notes

PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.

PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.

I2S Electrical, Audio, and Protocol Testing Software Datasheet

Key features

  • A single tool for physical, protocol and audio analysis helps to cross examine the electrical, protocol, and audio layers.
  • The industry’s first and best Penta monitor (Spectrogram monitor, Audio monitor, Protocol monitor, Signal monitor, and Eye diagram monitor) provides flexibility in analyzing the digital and analog audio data in a single window.
  • Cross-linking of the spectrogram, audio waveform, protocol data, analog physical layer signal, and eye diagram helps to identify the problem quickly.
  • Support for I2S, Left Justified, and Right Justified.
  • A wide range of automated timing measurements as per I2S standards helps to test compliance to I2S standard timing specifications.
  • Sophisticated protocol- and timing-based I2S triggering quickly to pinpoint the symptoms*1.
  • Oscilloscope setup assistant automatically performs oscilloscope setup to obtain accurate and reliable measurements.
  • Bus diagram and overlay of protocol data on the analog waveform in a signal monitor.
    Unprecedented “Search” capabilities locate unique events in thousands of protocol data.
  • Ability to play and store the uncompressed I2S waveform.
  • Comprehensive and customizable report generation.
  • Ability to export the analyzed data to .wav, Matlab, CSV, and text file formats for advanced analysis.

Key Specifications

I2S Electrical Validation, Audio and Protocol Decode Software

The I2S Electrical, Audio, and Protocol testing Software offers unprecedented cross-layer analysis tools and automation to improve quality and productivity while managing your schedules.

Protocol Decoding and Debugging Made Easy

PGY-I2S offers unmatched flexibility in performing exhaustive tests that help find problems quickly to ensure high-quality design.

PGY-I2S provides flexibility in analyzing the various I2S implementations and configurations.

I2S Electrical Validation, Audio and Protocol Decode Software

Powerful triggering capabilities*1 include I2S protocol and customized setup and hold triggers to help to identify and analyze the circuit problems.

I2S Electrical Validation, Audio and Protocol Decode Software

Compliance with a wide range of automated electrical measurements to the I2S standard helps you to address the physical layer interoperability problems.

The industry’s first and best Penta Monitor (Spectrogram monitor, Audio monitor, Signal monitor, Protocol monitor, and Eye diagram monitor) offers a single window to examine and analyze the I2S data in different domains.

I2S Electrical Validation, Audio and Protocol Decode Software

Spectral Monitor provides a deep insight into the transient audio behaviors in the design which are very hard to find in time-domain audio waveforms.

Audio Monitor provides a way to visually inspect the transmitted audio and play the sound.

The Protocol Monitor provides the left and right channel data listing and timing concerning trigger position.

The Signal Monitor provides insight into the transmitted I2S signals along with bus diagrams and overlaid decoded data.

Eye Diagram Monitor helps to understand the system performance, channel imperfections, and clock-to-data skew.

Penta Monitor along with the system utilities such as zoom, pan, un-do, fit to screen, cursors, and audio play provides flexibility to the design and debug engineers to identify the problem areas quicker.

I2S Electrical Validation, Audio and Protocol Decode Software

The unprecedented search capability compliments the trigger and helps to find problems in the physical layer, protocol layer, and audio layer faster.

I2S Electrical Validation, Audio and Protocol Decode Software

PGY-I2S software’s in-built automated report generator offers a very flexible report generation capability that helps to communicate the test reports effectively between fellow team members and management.

PGY-I2S Electrical, Audio, and Protocol Testing software combined with a Tektronix oscilloscope provide a single tool to debug and validate the I2S digital audio physical and protocol layers.

There are no standard measurement limits defined for SPI Bus for pass/fail tests. The limits are varying in nature depending on the SPI Bus speed. In order to characterize and validate SPI signals PGYSPI software provides a graphical measurement reference level setup to set the measurement reference level of SPI signals. These limits are automatically applied while making selected SPI measurements in PGY-SPI software and reduce test time by offering reliable measurements.

Applications

Debugging I2S protocol in:

  • Digital home appliances
  • Portable audio devices / MP3 players
  • Mobile smartphones / PDAs
  • Surveillance systems
  • Netbooks
  • Gaming machines

Characteristics

I2S Protocol Trigger*1– Standard I2S, LJ, RJ, Left or right data (equal and not equal), world long-only (I2S signal with a bit long LRCLK is not supported)

I2S Timing Trigger*1– WS setup time, WS hold time, Data setup time, Data hold time, clock high, clock low, clock to data delay, WS data delay.

I2S Measurements and compliance – Clock rise time, Clock fall time, Clock low period, Clock high period, Clock frequency, WS Setup time, WS hold time, Data setup time, Data hold time, Data –WS Delay time, Clock – Data delay time.

Displays – Spectrogram monitor, Audio Monitor, Protocol Monitor, Signal Monitor (Bus diagram), Eye Diagram Monitor

Protocol Display formats – Decimal, Signed (2’s complement), Hex, Binary, Octal, ASCII

Configuration settings – I2S, LJ, RJ, Data, Clock, WS, Suspicious Pop/Click source, Bit order(MSB/LSB first), world select (left = low/ Right =low), Data enable (Clock rise/ clock fall), Frame type(world long/ bit long), Mark / Space, Bits per data (Tx and Rx), Voltage reference (Vigh and Vlow), Audio sampling rate.

Display Utilities – Zoom, Pan, Undo, Cursor, link, Channel on/ off

Search

  • Protocol data search -Less than, greater than, equal, not equal, range,
  • Audio search – Mute, silence, Clip, bottom clip, glitch, pop,
  • Pattern search – Walking 1, walking 0, constant tone, staircase, constant,
  • Physical layer search- Clock rise time, Clock fall time, Clock low period, Clock high period, Clock frequency, WS Setup time, WS hold time, Data setup time, Data hold time, Data –WS Delay time, Clock – Data delay time
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