Logic Analyzer for Embedded Interfaces DataSheet

The DISCOVERY series PGY-LA-EMBD logic analyzer with protocol decode capabilities is designed to debug the logic and protocol issues faced by embedded design teams in consumer, industrial, home automation, health and education sectors.

Logic Analyzer for Embedded Interfaces DataSheet

PGY-LA-EMBD is an industry first logic analyzer in its category which enables engineers to debug timing problems and perform simultaneous protocol analysis of I2C, SPI and UART interfaces in embedded designs. This enables designers debug circuit level and system level problems quickly.

PGY-LA-EMBD offers 1GS/Sec asynchronous (timing) data and 100Mhz synchronous (state) data capture which makes it an ideal debug tool to address the digital design problems. Designers can now easily analyze setup and hold time issues, glitches and synchronous data activities apart from analyzing protocol issues.
Current generation embedded designers need to collect data from multiple interfaces such as I2C, SPI and UART and process it to achieve optimal performance of their designs. Embedded design teams need to take timely action to meet the intended objectives of the product. PGY-LA-EMBD simultaneously decodes I2C, SPI and UART bus and displays the protocol activity
with time stamp information. PGY-LA-EMBD is an ideal instrument to debug the hardware and embedded software integration issues and optimize the software performance.
Multiple markers enable smart delta measurements which are key to designers. Zoom enables users to look at specific areas of the signal.


  • 10 channels with Protocol and Logic Analysis capability.
  • 1GS/Sec Timing (Asynchronous) Analysis
  • 100MHz State (Synchronous) Analysis
  • Simultaneous Protocol Analysis of UART, SPI and I2C.
  • Detailed Trigger capabilities: Auto, Pattern, Protocol aware (UART, SPI and I2C) and timing (pulse width and delay).
  • Smart streaming of data from Protocol. Analyzer to host computer for long duration capture using USB3 interface.
  • Innovative easy to use Graphical user interface.
  • Error Analysis of Protocol packet
  • Provides timing, waveform, listing and Protocol listing views
  • Detailed filtering capability for protocol decoded data
  • PDF and CSV report format.
  • API support.

Easy Configuration

Users can easily configure the Logic Analyzer for embedded interfaces by either selecting Logic Analysis(LA) mode or Protocol Analysis (PA) mode or a combined (LA+PA) mode. This ensures a quick and easy way to configure the product and look at complex problems at system level either in Logic Analysis (State Analysis, Timing Analysis) or Protocol decoding or both. Save and Recall capability ensures designers can recall their custom setup details.

Multiple Views

Multiple domain Views provide the necessary complete view of all supported interfaces’ state, timing and protocol activity. Users can easily setup the analyzer to view timing, logic and protocol decode views to enable easy insights to the design. User can set different trigger conditions from the setup menu to capture timing and protocol activity at specific events. The decoded results can be viewed in timing, logic and protocol listing window with auto correlation. This comprehensive view of information makes it industry’s best, offering an easy to use solution to debug the embedded interfaces protocol activity and analyze timing issues. Multiple cursors help designers to look into details of their design performance.

Timing View

Timing view is a unique capability of the PGY-LA-EMBD which enables designers to get detailed insights to their signals timing information. The timing view uses internal clock signal to plot the waveform. The flexible sampling rate selection enables designers to investigate Glitches which can cause issues in the functioning of their designs. Grouping feature enables designers to group various related signals for better viewing and analysis. Marker and Zoom features make it convenient to analyze any timing errors. Ability to analyze any point in the captured data record ensures easy debug and analysis over a long capture duration.

State View/Waveform Listing View

State view helps designers to see the actual signal behavior. Using the device clock as reference, it provides the plot of clock and data signals with bus diagram. Grouping of signals ensures designers have the flexibility to view signals together. All signals are time correlated to help look into setup and hold times, pulse width, missing data etc. which are very critical for digital designs as designers look to optimize their codes.

Protocol Decode View

Protocol Activity window provides the decoded packet information in each state and all packet details with error info in the packets. This gives the system level insight to the design teams. The individual protocol decodes windows based on selected interfaces ensures easy viewability for design teams. Selected frame in Protocol listing window will be auto correlated in timing view to view the timing information of the packet. Protocol errors will be highlighted to ensure designers are alerted to the same easily.

Powerful Trigger Capabilities

PGY-LA-EMBD supports Auto, pattern, Protocol aware and timing parameter trigger capabilities. Users can trigger on any of the Protocol packets. Comprehensive Trigger provides the flexibility to monitor different conditions.


Detailed analytics on various protocol to enable better analysis and provide additional insights to designers.


Report can be generated in PDF or CSV format with details of all the signal information, plots and custom details like name of the company, logo, tester name, date and time to ensure designers can document all details and share the report.




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