Logic Analyzer for Embedded Interfaces DataSheet

The Discovery logic analyzer series, PGY-LA-EMBD has the built-in capability to debug I2C, SPI, UART, I3C, SPMI, CAN/CAN FD, and RFFE protocols. This is a pc based logic analyzer designed for professional engineers. The Discovery logic analyzer is used to debug embedded systems, the logic analyzer not only reduces the workbench area but also allows it to have a very small form factor and can be used to debug failures in the field. The protocol decode capabilities are designed to debug the logic and protocol issues faced by embedded design teams in consumer, industrial, home automation, health, and education sectors.

Logic Analyzer for Embedded Interfaces DataSheet

PGY-LA-EMBD is an industry-first logic analyzer in its category which enables engineers to debug timing problems and perform simultaneous protocol analysis of I2C, SPI, UART, I3C, SPMI, CAN/CAN FD, and RFFE in embedded designs. This enables designers to debug circuit-level and system-level problems quickly.

PGY-LA-EMBD offers 1GS/Sec asynchronous (timing) data and 100Mhz synchronous (state) data capture which makes it an ideal debug tool to address digital design problems. Designers can now easily analyze setup and hold time issues, glitches, and synchronous data activities apart from analyzing protocol issues.
Current generation embedded designers need to collect data from multiple interfaces such as I2C, SPI, UART, I3C, SPMI, CAN/CAN FD, and RFFE and process it to achieve optimal performance of their designs. Embedded design teams need to take timely action to meet the intended objectives of the product. PGY-LA-EMBD simultaneously decodes I2C, SPI, UART, I3C, SPMI, CAN/CAN FD, and RFFE bus and displays the protocol activity with timestamp information. PGY-LA-EMBD is an ideal instrument to debug hardware and embedded software integration issues and optimize software performance.
Multiple markers enable smart delta measurements which are key to designers. Zoom enables users to look at specific areas of the signal.

Features:

  • 16 channels with Protocol and Logic Analysis capability.
  • 1GS/Sec Timing (Asynchronous) Analysis
  • 100MHz State (Synchronous) Analysis
  • Simultaneous Protocol Analysis of I2C- SPI-UART-I3C-SPMI, CAN/CAN FD,  and RFFE.
  • Detailed Trigger capabilities: Auto, Pattern, Protocol awareness (I2C, SPI, UART, I3C, SPMI, CAN/CAN FD, RFFE), and Timing (Pulse Width and Delay Trigger).
  • Smart streaming of data from Protocol. Analyzer to host computer for long-duration capture using USB3.0 interface.
  • Innovative easy-to-use Graphic user interface.
  • Error Analysis of Protocol packet
  • Provides timing, waveform, listing, and Protocol listing views
  • Detailed filtering capability for protocol-decoded data
  • PDF and CSV report format.
  • API support.

Easy Configuration

Easy Configuration

 

Users can easily configure the Logic Analyzer for embedded interfaces by either selecting Logic Analysis(LA) mode or Protocol Analysis (PA) mode or a combined (LA+PA) mode. This ensures a quick and easy way to configure the product and look at complex problems at the system level either in Logic Analysis (State Analysis, Timing Analysis), or Protocol decoding, or both. Save and Recall capability ensures designers can recall their custom setup details.

Multiple Views

Multiple domain Views provide the necessary complete view of all supported interfaces’ state, timing and protocol activity. Users can easily set up the analyzer to view timing, logic, and protocol decode views to enable easy insights into the design. Users can set different trigger conditions from the setup menu to capture timing and protocol activity at specific events. The decoded results can be viewed in the timing, logic, and protocol listing window with autocorrelation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the embedded interfaces protocol activity and analyze timing issues. Multiple cursors help designers to look into details of their design performance.

Timing View

 

Timing view is a unique capability of the PGY-LA-EMBD which enables designers to get detailed insights into their signals’ timing information. The timing view uses an internal clock signal to plot the waveform. The flexible sampling rate selection enables designers to investigate Glitches that can cause issues in the functioning of their designs. The grouping feature enables designers to group various related signals for better viewing and analysis. Marker and Zoom features make it convenient to analyze any timing errors. The ability to analyze any point in the captured data record ensures easy debugging and analysis over a long capture duration.

State View/Waveform Listing View

State View/Waveform Listing View

State view helps designers to see the actual signal behavior. Using the device clock as a reference, it provides the plot of the clock and data signals with a bus diagram. Grouping of signals ensures designers have the flexibility to view signals together. All signals are time-correlated to help look into setup and hold times, pulse width, missing data, etc. which are very critical for digital designs as designers look to optimize their codes.

Protocol Decode View

 

The protocol Activity window provides the decoded packet information in each state and all packet details with error info in the packets. This gives system-level insight to the design teams. The individual protocol decodes windows based on selected interfaces ensuring easy viewability for design teams. The selected frame in the Protocol listing window will be autocorrelated in the timing view to view the timing information of the packet. Protocol errors will be highlighted to ensure designers are alerted to the same easily.

Powerful Trigger Capabilities

 

PGY-LA-EMBD supports Auto, pattern, Protocol awareness, and timing parameter trigger capabilities. Users can trigger any of the Protocol packets. Comprehensive Trigger provides the flexibility to monitor different conditions.

Analytics

Detailed analytics on the various protocol to enable better analysis and provide additional insights to designers.

Report

The report can be generated in PDF or CSV format with details of all the signal information, plots, and custom details like the name of the company, logo, tester name, date, and time to ensure designers can document all details and share the report.

 

 

Specifications

Logic analyzer

 

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