UFS 4.0 Protocol Analyzer
Product
Overview
Datasheet
Presentation
Application
Notes
PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.
PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.
eMMC and SD/SDIO Electrical Validation and Protocol Decode Software Datasheet
Key features
- eMMC and SD (UHS-I) electrical measurements and Protocol testing software conform to eMMC version 4.51 and 5.0 and SD version 3.01 specification
- Supports SDR and DDR and Boot mode for electrical measurement and Protocol Decode
- eMMC/SD/SDIO Protocol Aware Trigger features
- The software automatically identifies the read and write operations using CMD and applies the electrical parameter limits accordingly.
- Detail View provides efficient debugging capability by correlating the analog waveform, protocol messages, and electrical measurements for each protocol packet in a single view
- Protocol View lists the protocol activities in the sequential form to assist designers to know the host and card transactions
- Timestamp at the end of the command token and time stamp at beginning of the response token in Protocol View enables the designer to comply with specifications and locate any anomaly in timing between host and card
- The software displays the details of command and response in Protocol View and list the errors messages in card status for quick analysis
- Supports cursor-based measurements for manual custom measurements
- Ability to store the eMMC and SD protocol data in CSV and txt format
- Utility features like zoom, undo, and fit to screen for easy maneuvering of the waveforms while debugging the cause of the problem in Detail View makes it easy to use tool
- The software seamlessly integrates with Tektronix windows based oscilloscope and supports live signal analysis using live channels of the oscilloscope
- Supports data analysis for long record length and more acquisition memory of oscilloscope enables analysis of protocol events for longer duration
- Report generation in pdf format
- Supports WFM and isf file formats of Tektronix oscilloscope for offline analysis
Key Specifications
Applications
2. eMMC and SD (UHS-I) Electrical Compliance Test ( Supports eMMC4.42, 4.51, and 5.0 & SD3.01)
3. Correlation of Analog waveform, Protocol activities, and Electrical Measurements
Seamless Integration with Tektronix Oscilloscope
PGY- MMC and SD Electrical Validation and Protocol Decode Software run inside the Tektronix high-performance windows oscilloscopes. Automatically imports the data from oscilloscopes live channels. Also supports Tektronix .wfm and .isf file formats. This enables live and offline testing of eMMC and SD Signals.
- Provides the flexibility to select the type of Card interface to be tested and related Bus speed modes
- Flexibility select necessary or all electrical measurements
- Save and recall application setup for repetitive testing at different times
- Supports single and continuous test modes using oscilloscope live data
- Online help
eMMC/SD/SDIO Protocol Aware
For efficient testing and debugging of eMMC/SD/SDIO, it is important to capture signals in the right condition. PGY-MMCSD software provides protocol aware triggering along the serial pattern trigger option of the oscilloscope to capture signals at specific events in the CMD line.
- Flexibility to trigger on command or response
- Offers all the standard triggers patterns with command and Response
- Flexibility to edit trigger pattern
Automated Electrical Validation and Protocol Decode Software
As per the specification of eMMC and SD, the measurement limits are different for reading and writing operations. The PGY-MMC-SD measurement algorithms automatically find the read and write operations and validate with the respective limits. This enables you to save time in identifying the read and write operation and isolating any compliance issues.
- Lists electrical measurements with mean, minimum, and maximum values measured for the entire acquired waveform
- Indicates if the measurement exceeds the min or max limits by the orange color
- The lower and Upper limits of the electrical measurements are compared against measured values
- Supports Electrical Measurements as per eMMC 4.41 and 4.51 and UHS3.1 Specification
- Automated identification read and write operation and apply electrical limits as per eMMC and UHS-I specification
Timing Parameters between CMD, Response, and Data
eMMC specifies the minimum and maximum cycles to present between the host and device to ensure interoperability. PGY-MMC-SD analyzes the data for these specifications and offers results.
Protocol View
PGY-MMC-SD software lists all the protocol activity between the host and card. Engineers can now quickly view the command and its corresponding response from the card. Selected protocol activity details are listed on the right side of the list table. Now Engineers can know the errors reported by card or any other message to host without struggling to know the content of each message.
Characterization of PHY layer by custom limit setup
PGY-MMC-SD is not just for standard electrical compliance testing, you can also vary the limits and test your device with custom limits. The intuitive limits and reference level setup allows you to configure the limits and reference levels for your custom testing needs. This enables you to test your device beyond the specification and characterize it.
Powerful Debug environment: Detail view
In Detail View, engineers can view the analog waveform, details of the protocol, and electrical measurements in a single view. If there is any failure in electrical measurement or error in protocol messages, designers can quickly correlate the protocol data with analog waveforms. These protocol errors can be caused due to the failure in electrical measurements. Users can select any row in the detail view; the corresponding analog waveform will be zoomed in and displayed. In the same row, engineers can view all the electrical measurements corresponding to the selected row. Utility features such as zoom, cursors, and markers make custom measurements while debugging.
Detail view provides the following capabilities:
- Plots the acquired waveform in the waveform view window
- Lists all decoded command and response tokens in each row in the decode table
- Identifies of type of command and response for easy protocol interpretation
- Lists respective electrical measurements for command and response for each row
- Selected Protocol command or response’s related analog waveform is plotted in a window.
- Bus Diagram view overlays protocol data for the selected row along with waveform
- Snap button enables storing selected waveform window for report generation purpose
- Zoom, fit to screen, pan, undo, vertical and horizontal cursors enables quick analysis and measurement of electrical signals
Industry First Decoding of CMD and Data Signals:
PGY-MMC-SD leverages powerful capabilities of Digital Channels of MSO70000/5000 series oscilloscope to provide industry decoding of data signals in eMMC and UHS-I.
Protocol test:
PGY-MMC-SD software automatically checks for Protocol Integrity. This allows a very easy method of ensuring protocol packets are as per protocol specifications of eMMC, and UHS-I Specifications.
Electrical measurements for eMMC and SD Bus
| eMMC-HS DDR Measurements | Clock Frequency | Clock Low Time |
| Clock Rise Time | Clock Rise Time | |
| Clock Duty Cycle | Clock Duty Cycle | |
| Output Data Falling Time | Output Data Falling Time | |
| Input Setup Time | Input Setup Time | |
| Input Data Rising Time | Input Data Falling Time | |
| eMMC-HS SDR Measurements | Clock Frequency | Clock Low Time |
| Clock Rise Time | Clock Fall Time | |
| Output Data Falling Time | Output Data Rising Time | |
| Input Setup Time | Output Delay Time | |
| Input Data Falling Time | ||
| eMMC HS-BC Measurements | Clock Frequency | Clock Low Time |
| Clock Rise Time | Clock Fall Time | |
| Clock Duty Cycle | Output Setup Time | |
| Output Hold Time | Output Delay Time | |
| Input Setup Time | Input Hold Time | |
| eMMC HS-200 Measurements | Clock Period | Data Read Setup Time |
| Clock Rise Time | Data Read Hold Time | |
| Clock Fall Time | Command Output Delay | |
| Clock Duty Cycle | Data Write-Output Delay | |
| Response Setup Time | Command Valid Window | |
| Response Hold Time | Data Write Valid Window | |
| SD-DDR Measurements | Clock Frequency | Clock Low Time |
| Clock Rise Time | Clock Fall Time | |
| Clock Duty Cycle | Output Setup Time | |
| Output Delay Time | Input Hold Time | |
| Input Setup Time | ||
| Bus Speed | Supports all Data speeds; Limited by oscilloscope Bandwidth | |
| Protocol Decide | Protocol View and Detail View | |
| Waveforms Plots | Analog signals plotted with Bus diagram in for Protocol format for correlation of PHY information to Protocol data | |
| Report Generation | PDF format report generation | |
| Export of Data | Export to CSV and TXT format | |
| Oscilloscope file format | WFM and ISF file format of Tektronix oscilloscope | |
