UFS 4.0 Protocol Analyzer
Product
Overview
Datasheet
Presentation
Application
Notes
PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.
PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.
I2C/SPI Exerciser and Protocol Analyzer Datasheet
Key features
- Supports I2C Specifications
- Supports SPI Specifications
- Ability to configure it as Master/Slave
- Generate different I2C/SPI Packets
- Variable data speeds
- Generate I2C/SPI traffic and protocol decode of the bus
- A timing diagram of the protocol decoded bus
- Listing view of protocol activity
- Ability to write exerciser script to combine multiple frame generation at different data speeds
- USB 2/3 host computer interface
- Continuous streaming of protocol activity to host system HDD/SSD
- API support for automation in python or C#
Comprehensive Protocol Analysis using Multi-View
Multidomain View provides the complete view of I2C or SPI Protocol activity in a single GUI. Users can easily set up the analyzer to passively monitor or use the exerciser to generate I2C or SPI traffic using a GUI or script. Users can set different trigger conditions from the setup menu to capture Protocol activity at a specific event and decode the transition between Master and Slave. The decoded results can be viewed in the timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it the industry best, offering an easy-to-use solution to debug the I2C or SPI protocol activity. Continuous streaming protocol activity to host system HDD/SSD ensures seamless roll mode operation without the need to recapture data when DUT/s are set to different states thereby saving test times.
Exerciser:
PGY- I2C/SPI -EX-PD supports I2C or SPI traffic generation using GUI and Script. Users can generate traffic using the GUI to test the DUT. Script-based GUI provides flexibility to emulate the complete expected traffic in real-time.
Timing Diagram and Protocol Listing View
The timing view provides the plot of the Clock and data signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors.
The protocol window provides the decoded packet information in each state and all packet details. The selected frame in the Protocol listing window will be autocorrelated in the timing view to view the timing information of the packet.
Powerful Trigger Capabilities
PGY-I2C/SPI-EX-PD supports simple trigger capabilities. The analyzer can trigger on any of the Protocol packets. Advanced Trigger provides the flexibility to monitor Multiple trigger conditions and can set multiple state trigger machines. Users can initiate a timer and trigger onset timer values.
Key Specifications
Specifications
