I2C represents Inter-Integrated Circuit. I2C is a straightforward two-wire sequential convention used to convey between two devices or chips in an implanted framework. I2C has two lines SCL and SDA, SCL is utilized for clock and SDA is utilized for information. A between coordinated circuit (I2C) is a multi-master sequential bus that associates low-speed peripherals to a motherboard, cell phone, inserted framework or other electronic devices. Also called a two-wire interface.
I2C can move information between a focal processor and numerous ICs on a similar circuit board utilizing only two normal wires and it is broadly taken on for brief distance simultaneous sequential correspondence between microcontrollers, sensor clusters, shows, IoT devices, EEPROMs and so on. The I2C multi master bus comprises of two dynamic wires (Serial Data/SDA and Serial Clock/SCL) and information is moved one small step at a time along a solitary wire.
I2C configuration has a location/address space of 7 bit and it is basically utilized in bus speed modes, for example, standard mode(100kbit/s) and quick mode(400kbit/s). There is a low speed mode(10kbit/s), yet self-assertive low clock frequencies are acknowledged, and the most recent overhauls have speeds up to 5mbit/s. Address space and the absolute bus capacitance restricts the quantity of hubs which can exist on a given I2C bus and furthermore limits the correspondence distance to not many meters.
The information that should be moved is shipped off the Serial Data Line (SDA) wire and is synchronized with the clock signal from Serial Clock Line (CL).
The two I2C bus lines are worked as open channel drivers. This implies that any gadget on the I2C organization can drive SDA and SCL low, yet they can’t drive them high. Subsequently, a draw up resistor is utilized for each bus line, to keep them positive(high) of course. By utilizing an open channel framework, the odds of shorting will be decreased.
The devices which are associated with the I2C bus are called masters or slaves. Just a masters stays dynamic on the I2C bus at any moment. Masters controls the SCL clock line and the SDA lines and speaks with the slave gadgets.
While moving information to or from a slave devices, the master indicates a 7-bit address which is relegated to the slave device on the SDA line and afterward continues the information move. In this way, correspondence is done viably between the Master devices and the slave devices. The information moving is done in messages, which are separated into edges of information. The message incorporates address outline that contains the binary address of the slave, start/stop conditions, read/compose pieces and ACK/NACK between every information outline.
Start Condition: In start condition, the SDA line switches from a high voltage (‘1’ bit) level to a low voltage level (‘0’ bit) before the SCL line switches from high to low.
Address Frame/Slave Address: A 7-bit sequence unique to each slave that identifies the slave when the master device needs to send/receive data.
Read/Write Bit: A single bit specifying whether the master is sending data to the slave (the bit is set to ‘0’) or requesting data from the slave (the bit is set to ‘1’)
ACK/NACK Bit: Each frame in a message is followed by an acknowledge/not-acknowledge bit. If the physical address of any slave device matches with the address sent by the master device, an ACK bit is returned to the sender from the receiving device. (if matches the bit is set to ‘0’ otherwise it remains ‘1’)
Stop Condition: When the required data blocks are transferred through the SDA line, the SDA line switches from a low voltage (‘0’ bit) level to a high voltage level (‘1’ bit) before the SCL line switches from high to low.
When the master device detects the ACK bit from the slave device, the first data frame is ready to be sent. The data frame comprises of 8 bits and is sent by the sender with the most significant bit first. Each data frame is immediately followed by an ACK/NACK bit and is set to ‘0’ by the receiver to verify that the frame has been received successfully. Otherwise, it remains at its default value ‘1’. Depending on who is sending the data, the ACK/NACK bit must be received by either the master device or the slave device before the next data frame can be sent.