SMBus vs I2C: Differences between SMBus and I2C bus protocols
Introduction
SMBus vs I2C: The Inter-Integrated Circuit (I2C) bus has been in the industry for more than four decades. The System Management Bus (abbreviated as SMBus) which is derived from I2C has been in the industry for close to three decades. There are various computer, industrial and other applications that use I2C and SMBus for communication. This blog covers the differences between SMBus Protocol and the I2C bus protocol (SMBus vs I2C).
SMBus – Introduction
SMBus was defined by Intel and Duracell in the year 1994. It is a two-wired, single-ended, half-duplex, synchronous protocol meant for low-speed and lightweight applications. SMBus is derived from I2C Bus, i.e., the physical layer of SMBus is the same as I2C Bus. But SDA (Serial Data) and SCL (Serial Clock) are named SMBDAT and SMBCLK in SMBus. SMBus is used for communication between various components in computer systems such as motherboards, batteries, temperature sensors, power management devices, sideband communication in PCIe, etc. This blog refers to version 3.2 of SMBus released in Jan 2022.
General Characteristics – SMBus
There are three different types of devices referred to in SMBus specification i.e., controllers, targets, and hosts.
- Controller: A controller device issues commands, generates the clocks, and terminates the transfer. There may be more than one controller on an SMBus.
- Target: A target device responds to its address and receives commands. The number of targets in a system is theoretically limited only by the number of available addresses.
- Host: A Host is a specialized controller that provides the main interface to the system’s CPU or system management processor. There may be at most one Host in a system.
Addressing: Any device that exists on the SMBus has a unique 7-bit target address. The 10-bit addressing is planned for the future.
Supply Voltage requirements:
The SMBus offers two classes of electrical interface specifications.
Low Power specification: For systems where conservation of energy is more important than bus speed, e.g., battery-powered systems.
High Power specification: For systems where higher bus speeds are needed, such as in computing equipment.
As per SMBus specification, the nominal supply voltage of devices attached to the bus may range from 1.8 V (1.62 V minimum) to 5.0 V (5.5 V maximum). This does not mean that an SMBus device must operate with any supply in the range of 1.62 V to 5.5 V.
There is no requirement that all devices on an SMBus be powered from the same supply voltage or supply voltages of the same value. If devices with different supply voltages are used, the SMBus signals must be pulled up to the highest supply voltage. SMBus devices with different bus voltages are shown in Figure-1.
Figure-1: SMBus branch with multiple devices
Note: VDD1 > VDD2.
* All Rs are optional.
SMBus vs I2C: Difference between SMBus and I2C Bus
The SMBus and I2C bus are very similar and are generally interoperable. Table-1 lists the comparison between I2C Bus and SMBus (SMBus vs I2C)
| I2C | SMBus | |
| Developed by | Philips Semiconductor | Intel and Duracell |
| Year Introduced | 1982 | 1994 |
| Bus Architecture | Multi-Master, Multi-Slave | Multi-Master, Multi-Slave |
| Data Lines | SDA – Serial Data
SCL – Serial Clock |
SMBDAT – Serial Data
SMBCLK – Serial Clock |
| Communication Type | Synchronous | Synchronous |
| Data Transfer Mode | Half-Duplex | Half-Duplex |
| Interface Type | Open Drain | Open Drain |
| Minimum Clock Speed | DC | 10 KHz |
| Maximum Clock Speed
(Different speed modes) |
1.Standard Mode: DC to 100 KHz 2.Fast Mode: DC to 400 KHz 3.Fast Mode+: DC to 1 MHz 4. High-Speed mode: DC to 3.4 MHz 5. Ultra-fast mode: DC to 5.0 MHz (Unidirectional) |
Supports 3 different speeds.
1. 10 KHz – 100 KHz 2. 10 KHz – 400 KHz 3. 10 KHz – 1 MHz |
| Addressing | 7-bit or 10-bit addressing | 7-bit addressing |
| ACK by a slave for Address | Not always required always | Always required |
| Error Checking | Basic error detection (ACK / NACK) | Basic error checking and CRC |
| Clock Stretching | Supported (No time Limits) | Supported (up to Timeout) |
| Time out | No | Yes (Min: 25ms, Max: 35ms) |
| Nominal bus Voltage | – | 1.8 – 5.0 V |
| VIH (Min) | 0.7 x VDD | 1.35 V |
| VIL (Max) | 0.3 x VDD | 0.8 V |
| Support Address Resolution Protocol (ARP) | No | Yes |
| Alert Signal | No | Optional (SMBALERT#) |
Table -1: Difference between SMBus and I2C Bus (SMBus vs I2C)
VDD and Threshold Voltage difference
The I2C Protocol specification requires that VIH be 70% of VDD and VIL be 30% of VDD The SMBus V3.0 specification has fixed thresholds. VIL is set to 0.8 V and VIH is set to 1.35V. Though there is a difference in logical voltage thresholds, doesn’t affect the interoperability between the devices for the supply voltages permitted by SMBus specification.
Number of Masters and Slaves
Both I2C Bus and SMBus support Multi-Master, Multi-Slave architecture. Factors such as electrical loading, clock speed, and bus capacitance affect the number of devices that can be connected to the bus. 10-bit addressing is reserved for future implementation in SMBus. There are few addresses reserved for future use and the actual number will be lesser.
Minimum and Maximum Bus Speed
I2C doesn’t specify the minimum Clock speed i.e., the controller may hold the clock line Low forever which is considered valid. SMBus is required to have a minimum clock speed of 10 KHz. SMBus supports 100 KHz, 400 KHz, and 1 MHz. I2C supports five different bus modes namely Standard (100 KHz), Fast (400 KHz), Fast Mode+ (1 MHz), High-Speed Mode (3.4 MHz) in bi-directional mode, and Ultrafast mode (5.0 MHz) in unidirectional mode.
Address Acknowledge: The I2C specifications do not require that a device always acknowledge its address. If a device does not acknowledge its address, it would be difficult for the system controller to know if the target device is busy, has failed, or has been removed from the bus.
To prevent this confusion, the SMBus specifications require that an SMBus device always acknowledge its address. Figure-2 is the snapshot of the SMBus protocol frame format.
Figure-2: SMBus protocol frame format
After the START condition (“S”), the master places the 7-bit address of the slave device it wants to address on the bus. The address is 7 bits long followed by an eighth bit indicating the direction of the data transfer (R/W#); a ZERO indicates a transmission (WRITE) while a ONE indicates a request for data (READ). A data transfer is always terminated by a STOP (P) condition generated by the master.
Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an acknowledge bit. Bytes are transferred with the most significant bit (MSB) first.
SMBus Protocols
The I2C specification specifies only how to move bytes from one device to another. There is no standard on the structure of messages and packets. The SMBus specification defines command-oriented protocols that must be used when one SMBus device communicates with another. Examples of these protocols are WRITE WORD or READ 32.
Not all I2C devices will support all the SMBus transaction protocols.
REPEATED START Condition
As part of the SMBus protocols for reading data from a device the controller generally uses a REPEATED START condition. An attempt to use an SMBus protocol with a repeated START condition to read data from an I2C device may yield unexpected results.
SMBus Low Power Version
For applications that require low power such as in battery-operated systems, the SMBus specification has a Low Power class. I2C does not have a similar specification.
Maximum Clock Stretching and Device Timeout
Unlike I2C Bus, the SMBus specification places limits on the maximum amount of time a controller may extend the clock low time within each byte of a message and the total time a target device may extend the clock low time within each message.
A further SMBus restriction on the bus operation is a timeout (Minimum: 25ms and Maximum: 35ms) after which the bus is presumed hung. All devices attached to the bus must reset their I/O interface and make ready to receive a START condition.
Packet Error Checking (PEC)
The PEC is a CRC-8 error-checking byte, calculated on all the message bytes (including addresses and read/write bits). The PEC is appended as the last byte to the message by the device that supplied the last data byte. The PEC mechanism improves reliability and communication robustness.
Address Resolution Protocol (ARP)
The conflict in devices having the same static address on the SMBus can be resolved by assigning dynamically a new unique address to each target device using Address Resolution Protocol (ARP). The ARP possesses the following attributes:
- Address assignment utilizes the standard SMBus physical layer arbitration mechanism.
- Assigned addresses remain constant while device power is applied; address retention through device power loss is also allowed.
- Any SMBus controller can enumerate the bus.
- For address assignment, each device must implement a Unique Device Identifier (UDID).
SMBALERT#: This is an optional interrupt signal from the target device that can signal a controller that it wants to talk. The controller processes the interrupt and simultaneously accesses all SMBALERT# devices through the Alert Response Address (ARA: A broadcast address used by the controller or Host as part of the Alert Response Protocol). Only the device(s) which pulled SMBALERT# low will acknowledge the Alert Response Address.
Conclusion:
SMBus is backward compatible with the I2C bus despite the differences discussed above. It is worth noting that the choice of a protocol (like SMBus, I2C, or any protocol) for an application depends on factors like the architecture of the protocol at various communication layer levels, mode of data transfer, rate of data transfer, power consumption, ease of implementation, design cost, number of nodes that can be connected on the bus (Masters and Slaves), scalability, ease of integration, reliability (error handling), data security, compatibility with earlier (or) future versions, etc.
Useful Links:
SMBus Protocol Exerciser and Analyzer I2C/SPI Protocol Exerciser and Analyzer
About the author:
Karthikeyan Mahalingam is Sr. Manager, Product Management at Prodigy Technovations. He graduated from Bharathidasan University in 1998 with a Bachelor’s Degree in Electronics and Communications Engineering. He completed the Executive Management Program at Santa Clara’s Leavey School of Business in 2013. His interests and expertise include Firmware development, Motion Control, Communications Protocol, Product Development, and Client engagement.
