SDIO Tester Exerciser and Protocol Analyzer
PGY-SDIO-Tester is a SDIO Protocol Exerciser and Analyzer platform provides flexibility to emulate a SDIO host or device to validate the SOC or SDIO devices silicon devices to its functional performance. PGY-SDIO-tester can be configured as host or device and inject protocol traffic to device under test and monitor the device undertest performance. PGY-SDIO-Tester also supports error injection capability.
This innovative solution enables the validation engineers to run test cases to test different specifications and make all protocol functional tests measurements. User can write custom test cases using the test script which is easy to use.
PGY-SDIO-Tester interfaces to host computer using USB3.0 interface. User can configure the PGY-SDIO-Tester as a host or device. Product provides flexibility to write custom scripting the test cases to analyze the SDIO Protocol test cases to the performance of device under test. PGY-SDIO-Tester can inject error packets depending upon the test scenario.
Key features & Benefits
- Expected operating speed SDIO protocol is 50MHz based on device under test setup
- Can be configured as either SDIO host or device
- Generate different SDIO protocol packets based on the user need
- Basic test cases are provided as default feature
- Error injection capability
- Tolerance testing of devices outside the protocol specification
- Protocol Decoding of Command Signal and Data blocks of acquired with CRC check
- Upgradable to electrical compliance test mode
- Flexibility to vary the clock, CMD and data signals timing parameters
- Supports API for full test automation
- Report Generation with test results
- Customized Test Reports
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