Job Summary:

This is a full-time on-site role for a Senior FPGA RTL Design Engineer. The Senior FPGA RTL Design Engineer will be responsible for performing digital signal processing, debugging issues, and designing RTL for complex projects. The engineer will collaborate with cross-functional teams to develop and execute FPGA-based solutions.

Key Responsibilities:

• Expertise in Digital Signal Processing, Signal Processing, and RTL Design.
• 4 to 5 year experience design Verilog code/ implementing and successfully testing the IP in hardware.
• Strong debugging skills and experience in analyzing and resolving issues
• Bachelor’s or Master’s degree in Electrical Engineering or a related field
• Experience with FPGA development tools and methodologies
• Knowledge of industry standards and protocols such as PCIe, UFS, I3C, SPMI, RFFE
• Ability to work effectively in a team environment
• Excellent problem-solving and communication skills
• Experience in the semiconductor industry is a plus

Must have hands-on experience with FPGA debugging tools and test & measurement instruments such as oscilloscope and Logic Analyzer