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About SPMI Protocol:

The System Power Management Interface Protocol (SPMI Protocol ) is a MIPI standard interface that connects the integrated Power Controller (PC) of a System-on-Chip (SoC) processor system with one or more Power Management Integrated Circuits (PMIC) voltage regulation systems. SPMI Protocol enables systems to dynamically adjust the supply and substrate bias voltages of the voltage domains inside the SoC using a single SPMI Protocol bus.

Who should Attend :

Design Engineers, Test Engineers, Post Silicon Validation engineers, System design engineers, Engineering managers, Application Engineers, SoC Emulation engineers, RTL Engineers, Firmware Engineers, and Hardware Engineers, etc

Webinar Agenda:

This webinar will present at high-level MIPI Alliance specification  SPMI 1.0  (System Power management Interface) and SPMI 2.0. Designers can obtain an Overview of SPMI and for detailed study refer to the MIPI Alliance specification document.

  1. SPMI Protocol Basics
  2. Overview of SPMI Protocol
  3. Pain points and challenges of the SPMI Protocol Analysis
  4. SPMI Traffix generation with error injection
  5. Capture the SPMI Protocol and Analysis
  6. Live Product Demo


Speaker Profile: Mr.Prajeesh P

Prajeesh has extensive research-oriented work experience in FPGA-based product development, RTL design, and ASIC IP design. He has rich system-level knowledge and his experience covers specification/requirements to product delivery including requirement analysis, architecture definition, component selection, etc. He has worked in multi-national product companies such as Delphi, Bosch, Synopsys, Samsung, Cambium Networks before joining Prodigy.


Speaker Profile: Mr.Anuj

Anuj is a FPGA Design Engineer who has worked on Prodigy’s System Power Management Interface (SPMI) Exerciser and Protocol Analyzer product (PGY-SPMI-EX-PD). Anuj has deep understanding of SPMI v1.0/v2.0 Specification and SPMI Protocol Implementation Conformance Statement (PICS) for SPMI v2.0 Specification. He has hands-on experience in debugging and fixing hardware issues reported during product development and has rich experience in resolving customer issues during product evaluation.

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