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    About QSPI Protocol:

    QSPI Interface uses 6 pins in total, 4 data lines, ( this is why the name is QUAD). One clock signal and one chip were selected. It allows us to extend the memory space of our embedded system., For example, graphic data or additional Quad because it is possible to execute code directly from QUAD SPI memory.
    Many systems today need additional external memory ie SRAM flash. MicroControllers are using large parallel interfaces to support such requirements to create complex routing lanes. This cumbersome interface can be improved by saving board space and freeing pins by using QSPI.

    Who should Attend :

    Design Engineers, Test Engineers, Post Silicon Validation engineers, System design engineers, Engineering managers, Application Engineers, SoC Emulation engineers, RTL Engineers, Firmware Engineers, and Hardware Engineers, etc

    Webinar Agenda:

    In the webinar, you will learn about QSPI Protocol Analysis and Debug. This webinar is for all the engineers working on Pre-silicon and post-silicon validation, this will help you debug complex engineering designs.

    1. QSPI Protocol Basics
    2. Overview of QSPI Protocol
    3. Pain points and challenges of the QSPI Protocol Analysis
    4. Capture the QSPI Protocol and Analysis
    5. Live Product Demo

    Speaker Profile: Mr. Vibhav Karki

    Speaker Profile: Mr. Manjunath

    Speaker Profile: Mr. Anuj

    Vibhav has over 13 years of industry experience with deep expertise in the development of system software and applications. He is actively involved in the architecture, design, and implementation of various high-speed protocols.  Vibhav has been with Prodigy Technovations for 7 years now. Vibhav graduated with a B.E from Visvesvaraya Technological University.

    Manjunath is a senior software engineer who worked on Prodigy’s I3C Exerciser and Protocol Analyzer (PGY-I3C-EX-PD). Manjunath has over 5+ years of experience in software desktop applications and has a deep understanding of I3C Specification and Conformance Test Suite (CTS). He has hands-on experience in debugging and fixing software issues during product development and has good experience in resolving customer issues during product evaluation.

    Anuj is an FPGA Design Engineer who has worked on Prodigy’s QSPI Exerciser and Protocol Analyzer product. Anuj has a deep understanding of QSPI Protocol Implementation. He has hands-on experience in debugging and fixing hardware issues reported during product development and has rich experience in resolving customer issues during product evaluation.

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