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The ALINT-PRO Static Design Verification solution includes DO-254 HDL Ruleset targeted for safety-critical designs that require DO-254 compliance. Recently, this DO-254 Ruleset was enhanced with more than 80 new rules, adding a significant amount of code checks for Verilog and VHDL-based designs relevant to coding practices, clock domain crossings, safe synthesis, and code reviews.
Who should Attend :
Design Engineers, Test Engineers, Post Silicon Validation engineers, System design engineers, Engineering managers, Application Engineers, SoC Emulation engineers, RTL Engineers, Firmware Engineers, and Hardware Engineers, etc
What will you learn:
This webinar will provide an overview of the newly added DO-254 rules, from their specification to implementation and code examples. We will also discuss the available tool qualification data package for ALINT-PRO.
Webinar Agenda :
- New DO-254 coding rules for VHDL and Verilog
- Rule examples
- Coding Practices
- Clock Domain Crossings
- Safe Synthesis
- Code Reviews
- Tool Qualification Data Package
- Q & A
Design Verification Technologist
Alex accumulated 25 years of hands-on experience in various aspects of ASIC and FPGA design and verification. His employees’ list includes IBM, Nortel, Ericsson, and Synopsys Inc. As Verification Prime for a multi-million gates project, he combined various verification methods – LINT, Formal Property checking, dynamic simulation, and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.