UFS 4.0 Protocol Analyzer

UFS Protocol Analyzer (PGY-UFS 4.0-PA) is the Protocol Analyzer with multiple features that offers protocol data capture and debug of data across MPHY, UniPro and UFS protocol layers. PGY-UFS4.X-PA, UFS Protocol Analyzer, allows for instantaneous decoding of UFS, UniPro and MPHY layers with flexibility to correlate decoded data across these protocol layers. PGY-UFS 4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS 4.0 Protocol Analyzer.

UFS 4.0 Protocol Analyzer

PGY-UFS 4.0-PA supports PWMG1 to HSG5B data rates and two TX, two RX lane decode. The active probe has minimum electrical loading on device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS 4.0- PA Protocol Analyzer support two lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.

 

PGY-UFS 4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro and MPHY layers with a correlation to MPHY, UniPro and UFS layers.

 

Features

The product features are as follows:

  • Supports PWM G1 to G7 and HS G1,2,3, 4, 5 Rate A and B Series
  • Supports one/two data lanes (2 TX and 2 RX)
  • Flexibility to capture very large data using continuous streaming of Protocol data to host computer
  • with 16GB Internal acquisition memory field upgradeable up to 64GB
  • Hardware-based resizable circular buffer with pre/post trigger
  • Flexibility to decode selected data from 16GB buffer
  • Solder down active probe provides high signal fidelity
  • Decoding at MPHY, UniPro, and UFS layers
  • Trigger-based on MPHY, UniPro, and UFS layers packet content
  • Trigger out a signal at trigger event allows the triggering of other instruments such as oscilloscope
  • Interface to host system using USB 3.0
  • Flexibility to upgrade the hardware firmware using GbE interface provides easy field up gradation of FPGA firmware
  • Decoded data packets can be exported to txt file for further analysis
  • Lightweight and can be deployed for on-site/ field tests

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