The I3C serial bus interface is emerging as a chosen interface for all future sensor connectivity in mobile phone and automotive industries. This could also be chosen as a low-cost, reliable interface for future embedded electronic applications to address the new data-intensive applications.

The PGY-I3C-EX-PD is the leading instrument that enables the design and test engineers to test the I3C designs for their specifications by configuring the PGY-I3C-EX-PD as Master/Slave to generate I3C traffic with error injection capabilities and to decode I3C protocol packets.

Key Features

1. Supports v1.0/v1.1 Specifications

2. Ability to configure it as Master or Slave.

3. Ability to configure BCR, LVR, and DCR registers.

4. Simultaneously generate I3C traffic and Protocol decode of the Bus.

5. Optional Compliance Test Specifications (CTS) test script support.

6. Supports legacy I2C slaves and Master.

7. Generate different I3C SDR and HDR Packets.

8. Supports IBI and Hot Plug capabilities.

9. Error Injection such as CRC errors, parity errors, and ACK/NACK errors.

10. Variable I3C data speeds and duty cycle.

11. PMIC device support as per JEDEC DDR5 spec requirement.

12. Margin test capability: Voltage and timing variation.

13. Continuous streaming of protocol data between the instrument and host computer.

14. Timing diagram of Protocol decoded bus.

15. Listing view of Protocol activity.

16. Error Analysis in Protocol Decode.

17. Ability to write exerciser script to combine multiple data frame generation at different data speeds.

18. USB2/3 host computer interface.

19. API support for automation in Python or C++. 1 v1.1 supports only one lane commands

v1.1 supports only one lane commands

I3C Protocol Analyzer and Exerciser – FAQ Section

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