I3C Protocol Analyzer and Exerciser

I3C Protocol Analyzer (PGY-I3C-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between host and design under test. I3C Serial bus interface is emerging as a chosen interface for all future sensor connectivity in mobile phone and automotive Industry. This could also be chosen for low cost, reliable interface for future embedded electronic applications to address the new data intensive applications.

I3C Protocol Analyzer and Exerciser

PGY-I3C-EX-PD is the leading instrument that enables the design and test engineers to test the I3C designs for its specifications by configuring PGY-I3C-EX-ED as master/slave, generating I3C traffic with error injection capability and decoding I3C Protocol decode packets.

The product features are as follows:

  • Ability to configure it as Master or Slave
  • Ability to configure BCR, LVR and DCR registers
  • Supports legacy I2C slaves and Master
  • Generate different I3C and I2C SDR and HDR Packets
  • Flexibility to upgrade the unit TSP and TSL encoding (When it is available)
  • Error Injection such CRC errors, parity errors and ACK/NACK errors
  • Variable I3C data speeds
  • Simultaneously generate I3C traffic and Protocol decode of the Bus
  • Timing diagram of Protocol decoded bus
  • Listing view of Protocol activity
  • Error Analysis in Protocol Decode
  • State Machine view of the I3C packets
  • Ability to write exerciser script to combine multiple data frame generation at different data speeds
  • USB2/3 host computer interface
  • Flexibility to upgrade to the unit for evolving I3C Specification


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