I3C Protocol Analyzer and Exerciser
I3C serial bus interface is emerging as a chosen interface for all future speed connectivity in mobile phone, automotive, CXL, DDR5 memory, SSD, PMIC applications. This could also be chosen as a low-cost, reliable interface for future embedded electronic applications to address the new data-intensive applications. DMTF uses I3C as one of the base protocols to drive the MCTP transport layer and supports application-layer protocols such as NVMe-MI, SPDM, and PLDM.
The I3C Protocol Analyzer (PGY-I3C-EX-PD) is the leading instrument that enables the design and test engineers to test the I3C designs for its specifications by configuring the PGY-I3C-EX-PD as controller and/or target to generate I3C traffic with margin test, error injection capabilities, conformance tests and to decode I3C protocol packets with error analysis capabilities.
PGY-I3C-EX-PD has designed to support current and emerging applications in mobile, automotive, CXL, DDR5, SSD and PMIC applications. It supports multiple protocols on base I3C protocol such as MCTP, PLDM, SPDM and NVMe-MI. I3C Specification also supports multi lane so that user can drive more data between the controller and target.
PGY-I3C-EX-PD is upgradeable to dual and quad lane I3C Protocol Exerciser and Analysis capabilities to support future needs.
Key features
- Emulates
- I3C Controller and Target
- I3C Secondary Controller
- I2C Controller and target
- Specifications
- I3C v1.0, V1.1, V1.1.1, V1.2
- Traffic generation and protocol analysis
- SDR, HDR, TSL, TSP encoded I3C Protocol
- I2C Protocol
- Data Rate Support
- 1Hz to 12.5MHz
- Supports
- In-Band- Interrupt
- Hot Plug capabilities
- Error Injections
- CRC Errors
- Parity Errors
- ACK/NACK errors
- Different Protocol Over I3C
- MCTP, NVMe-MI
- SPDM, PLDM
- Optional Conformance Test Suite
- I3C-CTS V1.1
- MCTP-CTS
- NVMe-MI-CTS
- SPDM-CTS
- Margin Test
- Variable Datarate & Data Cycle
- Voltage & timing Variation
- Protocol Analysis
- Sniffer I3C & I2C
- Timing Plot with bus Diagram
- Advance Trigger
- Continuous streaming for buffer size
- Views
- Protocol Listing Window
- Timing Plot with bus Diagram
- Exerciser Scripting Window
- API Support
- Python and C++
- OS Support
- Windows
- Linux
- Mac OS
- Report
- HTML
- CVS Export
Applications
- Pre Silicon Validation
- Post Silicon validation
- CXL side Band Signal Validation
- SSD Side Band Signal Validation
- PMIC DDR5 JEDEC
- CTS Testing for I3C, MCTP, SPDM,
NVMe-MI
Multi-Domain View
Multi-domain View provides the complete view of I3C Protocol activity in a single GUI. Users can easily set up the analyzer to generate I3C/I2C traffic using the GUI or script. Users can set different trigger conditions from the setup menu to capture protocol activity at specific events and decode the transactions between the controller and target. The decoded results can be viewed in the timing diagram and protocol listing window with auto-correlation. This comprehensive view of information makes it an industry- best offering and an easy to-use solution to debug the I3C protocol activity.
Exerciser (Tester)
PGY-I3C-EX-PD has a high-performance flying cable with female header pin to meet the clock speed of 12.5MHz. This allows user to connect the instrument to device under test (DUT). The tester is controlled by PGY-I3C-EX-PD software which can run on Windows, Mac OS or Linux and enables driving traffic to DUT and analysis of the DUT Response. The tester can passively monitor the traffic in DUT if it is connected to a I3C Bus. PGY-I3C-EX-PD supports I3C/I2C traffic generation using GUI and Script. Users can perform simple traffic generation using the GUI to test the DUT. Script-based GUI provides flexibility to emulate and drive the expected traffic in real-world scenarios including error injections. Exerciser can easily add controller, secondary controller, internal targets, and external targets to create the test environment. User can write the script to emulate a controller or target.
Script description:
The script performs device enumeration by issuing the Broadcast ENTDAA CCC, which enables the controller to assign dynamic addresses to all connected targets. following which the controller sends a Directed GETPID command to retrieve the Provisional ID (PID) of the assigned target, ensuring proper device identification. Following this, the controller performs a private SDR write operation to transmit data into a specific register, and subsequently executes a private SDR read from the same register to validate the transaction by confirming that the written data has been correctly stored. The entire sequence is executed at a bus frequency of 500 kHz with a 50% duty cycle. Users can configure various timing parameters as per their test scenario.
Timing Diagram and Protocol Listing View
The timing view provides the plot of SCL and SDA signals with bus diagram information. Overlaying of protocol bits on the digital timing waveform helps in easy debugging of protocol decoded data. Cursor and Zoom features makes it convenient to analyze protocol in timing diagram view for any timing error.
The protocol window provides the decoded packet information in each state and all packet details with error info in the packet. The selected frame in the protocol listing window will be auto-correlated with the timing view to check the timing information of the packet.
Support for Legacy I2C and SM Bus over I2C
PGY-I3C-EX-PD unit supports legacy I2C devices on the I3C network. User can send I2C traffic targeting to I2C devices. User can configure I3C bus with I2C target.
User can drive SM Bus protocol traffic over I2C Protocol. Scripting in PGY-I3C-EX-PD is very exhaustive and it enables user to send any other application layer protocol packets on top of I2C or I3C protocol as payload of I2C protocol packet. I2C target will interpret this SM protocol and take necessary actions. SMBus Block Read command can be emulated using an I2C Read command to verify the transition. Below is a sample script illustrating this approach:
Script
Script:SysOD Freq:100 tLOW:50 tHIGH:50 tCAS:800
Script:Sys Freq:100 tHIGH:50 tLOW:50 tCO:10
Script:SysExtended tSU_STA:800 tSU_STO:800 I2CMode:OD
{
Script:Bus Frame:I2C Address:61 Transfer:WRITE Data:06 Stop:False
Script:Bus Frame:I2C Address:61 Transfer:READ DataCount:5
}
In the above script, the SMBus Block Read command is framed using standard I2C Write and Read operations.
Here, the first I2C Write with data 06 represents the Block Read CCC value, followed by a repeated start and an I2C Read with a data count (byte count) of 5 (user-configurable).
The overall sequence corresponds to the SMBus Block Read frame:
Start → Address → Write → Command Value → Repeated Start → Address → Read → Byte Count.
I3C Conformance Test Suite V1.1.1
I3C Working Group in MIPI Alliance has developed I3C Conformance Test suite(CTS) for controller and target. These test cases are developed such that any controller or target which passes all these test cases, are expected to inter operate with all the I3C devices in the market. PGY-I3C-EX-PD provides packaged optional tool, which enables user to conduct all these tests at ease. It will highlight failed test cases and provides the reason for failure making easy to debug. User can generate CTS test report for documentation purpose.
I3C-CTS in PGY-I3C-EX-PD has flexibility of dynamic address assignment using different commands, specify the clock frequency for test case, sweep the tests at different frequency by incremental steps. This tools reduces the learning curve of the CTS and faster time to market.
MCTP Protocol Decode, Scripting and Conformance Test Suite
Management Component Transport Protocol (MCTP) is a transport layer protocol and encapsulated in I3C Protocol. MCTP enables intercommunication among different devices in management controller, GPUs, CPUs and intelligent devices.
PGY-I3C-EX-PD enables designer and test engineer write the MCTP layer protocol script to generate MCTP over I3C traffic to validate the DUT performance. Also, Tester will decode the MCTP communication in a I3C bus.
Distributed Management Task Force (DMTF) has developed Conformance Test Suite (CTS) so that all the devices that support interoperate in real-world environment. PGY-I3C-EX PD supports all these test cases as a packaged tool where user can test DUT for MCTP-CTS at the click of a button. Test report will have CTS performance report and reason for failure if any test is failed.
PGY-I3C-EX-PD supports auto, simple, and advanced trigger capabilities. The analyzer can trigger any of the protocol packets such as broadcast, directed, or private messages. Advanced trigger provides the flexibility to monitor multiple trigger conditions and can set multiple state trigger machines.
NVMe-MI Protocol Decode, Scripting and Conformance Test Suite
PGY-I3C-EX-PD drives all these test cases traffic to DUT at a click of a button. The software analyses the DUT response for conformance to tests and report pass/fail status for each test case. It also provides a detail report for test case failures for easy debugging of the failed test cases.
The NVMe management Interface (NVMe-MI) commands
encapsulated in MCTP protocol enables the management of
solid-state drives (SSDs) enclosures independent of the operating system. NVMe-MI protocol used in out of band mode allows separate management controller (BMC) to communicate with SSDs and other peripherals using dedicated I3C interface. This ensures continuous management of system though the high-speed links that are not operating due to any issues.
PGY-I3C-EX-PD supports NVMe-MI Protocol scripting over MCTP transport layer protocol and drive the NVMe-MI traffic to DUT. The tester also decodes the NVMe-MI traffic in a System by sniffing the I3C BUS.
University of New Hampshire (UNH) IOL developed conformance test Suite cases so that NVMe-MI Protocol works reliably in configuration, health status polling and data length verifications.
PGY-I3C-EX-PD has optional NVMe-MI Conformance Test Suite. It supports all the mandatory test cases to test the SSDs which need to comply with NVMe-MI over I3C Protocol.
User Can Select each or all test cases and drive the NVMe-MI traffic to device under test. The software will automatically analyze the device response and provide pass/fail results.
The software will highlight failed test case in red and list the cause for failure so that design and test engineers quickly address the issue enabling faster time to market.
SPDM Protocol Decode, Scripting and Conformance Test Suite
Security Protocol and data Model (SPDM) is transmitted over MCTP. One of the lower layer protocol for MCTP is I3C. PGY-I3C-EX-PD supports SPDM over MCTP. SPDM enables the management controller to perform security functions such as discovery, authentication and measurement retrieval.
PGY-I3C-EX-PD supports SPDM over MCTP traffic generation to DUT. User can write their own custom scripts and drive the traffic to DUT. The tester analyzes the response from DUT and provides detailed protocol analysis
DMTF offers a list of SPDM Conformance Test Cases which are integrated with PGY-I3C-EX-PD. User can select each test case and drive the relevant SPDM Protocol traffic to the DUT using off the shelf test cases. The response of the DUT is analyzed and test result is reported by PGY-I3C-EX-PD. The tester can also generate the test report for records.
PLDM Protocol Scripting and Conformance Test Suite
Platform Level data Model (PLDM) over MCTP is emerging application for I3C protocol. PLDM application layer protocol is used for communication between components in server. PLDM carries out monitoring hardware, updating firmware, monitoring power states.
PGY-I3C-EX-PD supports PLDM protocol scripting analysis for easy testing of PLDM supported devices. User can generate PLDM traffic by easy to auto guided script and inject to the device under test (DUT). The tester analyzes this traffic and display response from the DUT and list the communication between tester and DUT.
PGY-I3C-EX-PD as a Sniffer
PGY-I3C-EX-PD also has a built in I3C and I2C Protocol Analysis capabilities. The instrument can be connected to I3C bus and use it as a protocol analyzer by passively sniffing the I3C bus. The instrument continuously captures I3C/I2C protocol traffic and streams to the host PC enabling the data capture for a long duration. It has a built-in powerful protocol aware trigger capabilities enabling the design and test engineers to capture the protocol traffic at a specific time.
Powerful Trigger Capabilities
PGY-I3C-EX-PD supports auto, simple and advanced trigger capabilities. The analyzer can trigger on any of the protocol packets such as broadcast, directed or private messages. Advanced trigger provides the flexibility to monitor multiple trigger conditions and can set multiple state trigger machines.
I3C Multilane Support in PGY-I3C-EX-PD
PGY-I3C-EX-PD supports dual and quad lane protocol exerciser and analysis capabilities. User has flexibility to procure one lane I3C exerciser solution and upgrade the hardware to dual or multilane as and when required.
The support for optional different application protocols, dual lane and quad lane can be field upgradable. This protects your investment in PGY-I3C-EX-PD over longer period of time. Prodigy Technovations is working continously with all the customers in supporting their needs and updating the software to meet our customer needs.
PGY-I3C-EX-PD Specification
Exerciser | |
Configurable | 1 Controller + 3 Target or |
I3C/I2C Traffic Generation | Custom I3C / I2C traffic generation (Simulate real world network traffic)Custom I3C/I2C traffic generation (Simulate real world network traffic) |
Transport and Application layer Protocols | MCTP, NVMe-MI, SPDM, PLDM |
Conformance Test Suite (CTS) | MCTP-CTS, MVMe-MI-CTS, SPDM-CTS |
SCL Frequency | 1Hz to 12.5MHz Note: Prodigy device supports up to 10MHz at 1V frequency as a target |
Configurable Voltage Level Drive | 0.9V to 3.4V Steps: 0.9-1.27V (In steps of 5mV) 1.27-1.95V (In steps of 10mV) 1.95-3.4V (In steps of 30mV) |
Heat Join | Yes, supported |
IBI | Yes, supported |
CCC Support | All CCC are supported in Controller Side. All CCC are supported in Target except SETXTIME, ENTTM, ENTAS* |
SCL Duty Cycle variation | User Defined (In Fine resolutions of 10ns) |
SCL & SDA Delay | User Defined (In Fine resolutions of 18ps) |
Delay between two messages | User Defined (In Fine resolutions of ns, us, ms and seconds) |
Error injection | S0 to S5 types of errors specified in BBC specifications CRC errors in DDR traffic. Preamble errors in DDR traffic ACK/NACK Errors (Slave) Master Abort. Non-Standard Frames. Non-Standard Start, Stop and HDR exit patterns, slave reset Save and Load Scripts. |
API Support | Support for Automation of operation using Python or C++ |
Protocol Analysis: | |
Supports | I3C & I2C protocol decode. Multilane decoding |
Protocol Views | Timing Diagram View Protocol Listing View Bus-Diagram to display Protocol packets with timing diagram plot |
Protocol Trigger | Auto (Trigger on any packet) Simple (Trigger on user defined I3C or I2C packet) |
Capture Duration | Continuous streaming Protocol Data to host HDD/SSD |
Protocol Error Report | S0 to S5 types of errors specified in the I3C specifications CRC errors in DDR traffic Preamble errors in DDR traffic ACK/NACK Errors (Target) Controller Abort Non-Standard frames Non-standard Start, Stop and HDR exit patterns. |
Host Connectivity | USB 3.0/2.0 interface |
I3C Validation Deep Dive - PGY-I3C-EX-PD
I3C Protocol Analyzer and Exerciser – FAQ Section
Yes, PGY-I3C-EX-PD has support for API using Python and C++.
The PGY-I3C-EX-PD unit is field upgradable using firmware upgrades.
During warranty, the first level support is offered over emails/phone/WebEx. If physical support/repair is required, the unit needs to be shipped back to Prodigy India office. Where if we find the hardware faulty, we will repair/replace the unit under warranty.
Yes, PGY-I3C-EX-PD will have support for CTS v1.1.1 under which almost 90 test cases are included. Being a contributing member to MIPI, we have our CTS suite ready with the provisional specs, but the final document is still under review and it is expected to be ratified by MIPI soon. Hence, the Opt CTS (v1.1) delivery is subject to MIPI ratification. Once released, this option will also be post purchase – field upgradable for all existing customers.
The bus voltage can be varied from 1.0 V to 3.3V in steps of 50mV.
The PGY-I3C-EX-PD comes with a standard 12 months return to Prodigy warranty on the hardware and 12 months software support. Upfront hardware warranty & software support extension is possible for additional 24 Months. Accessories, cables & Probes are covered under 90 days warranty for any manufacturing defect only.
PGY-I3C-EX-PD has support for 1 Master + 3 slaves or 1 Master + 1 Secondary master and 2 slaves internally.
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