PGY-RFFE-EX-PD is the leading instrument that enables the design and test engineers to test the RFFE interface for its specifications by configuring PGY-RFFE-EX-PD as master/slave, generating RFFE traffic with error injection capability, amplitude variation, and decoding RFFE Protocol decode packets.
The product features are as follows:
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Multi-domain View provides the complete view of RFFE Protocol activity in a single GUI. Users can easily set up the analyzer to generate RFFE traffic using a GUI or script. Users can set different trigger conditions from the setup menu to capture Protocol activity at specific events and decode the protocol transactions between Master and Slave. The decoded results can be viewed in the timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the RFFE protocol activity.
PGY-RFFE-EX-PD supports RFFE traffic generation using GUI and Script. Users can generate simple traffic generation using the GUI to test the DUT. Script-based GUI provides flexibility to emulate the complete expected traffic in the real-world including error injections. In this sample script user can generate RFFE traffic as below:
- Script line #4: REG Write to the slave with USID 5
- Script line #5: REG Read to the slave with USID 5
- Script line #8: EXT REG Write to the slave with USID 5
- Script line #9: EXT REG Read to the slave with USID 5
Timing Diagram and Protocol Listing View
The timing view provides the plot of SCLK and SDATA signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors.
The protocol window provides the decoded packet information in each state and all packet details. The selected frame in the Protocol listing window will be auto-correlated in the timing view to view the timing information of the packet.
Powerful Trigger Capabilities
PGY-RFFE-EX-PD supports auto, simple, and advanced trigger capabilities. The analyzer can trigger on any of the Protocol packets such as Ext. Reg. Write, Ext. Reg, read and so forth message. Advanced Trigger provides the flexibility to monitor multiple trigger conditions and can set multiple state trigger machines.
PGY-RFFE-EX-PD (v 2.0): RFFE Protocol Exerciser and Analyzer (v 2.0 specification supported)
PGY-RFFE-EX-PD (v2.1): RFFE Protocol Exerciser and Analyzer (v 2.1 specification supported)
PGY-RFFE-UPG (v2.0 to v 2.1): RFFE Protocol Exerciser and Analyzer (upgrade option from v 2.0 specification to v 2.1 specification)
Opt PICS: Protocol Implementation Compliance statement for v 2.1 specification
Deliverables Ordering Information
PGY-RFFE-EX-PD RFFE Protocol Exerciser and Analyzer
- PGY-RFFE-EX-PD Unit
- USB3.0 cable
- PGY-RFFE-EX-PD Software in CD
- 12V DC adopter
- Flying lead probe cable with female connector to connect to DUT