UFS 4.0 Protocol Analyzer
Product
Overview
Datasheet
Presentation
Application
Notes
PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.
PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.
PMBus Protocol Analyzer and Exerciser Datasheet
Key features
- Supports PMBus Specifications.
- Ability to configure it as Master/Slave.
- Variable data speeds.
- Generate PMbus traffic and protocol decode of the bus.
- A timing diagram of the protocol decoded bus.
- Listing view of protocol activity.
- Ability to write exerciser script to combine multiple frame generation at different data speeds.
- USB 2/3 host computer interface.
- Continuous streaming of protocol data to host computer to provide a large buffer.
- API support for automation in python or C++.
Multi-domain View
Multi-Domain View provides the complete view of PMBus Protocol activity in a single GUI. Users can easily set up the analyzer to generate PMBus traffic using a GUI or script. Users can set different trigger conditions from the setup menu to capture Protocol activity at specific events and decode the transition between Master and Slave. The decoded results can be viewed in the timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the PMBus protocol activity.
Exerciser
PGY-PMBus-EX-PD supports PMBus traffic generation using GUI and Script. Users can generate simple traffic generation using the GUI to test the DUT. Script-based GUI provides flexibility to emulate the complete expected traffic in the real world including error injections. In this sample script user can generate PMBus traffic as below:
Script line #1: Set system Frequency 1MHz, Duty cycle to 50%, CLK to data delay to 10ns
Script line #3: WRITE Transaction_Type
Script line #4: READ Transaction_Type
Timing Diagram and Protocol Listing View
The timing view provides the plot of SCL and SDA signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors.
Powerful Trigger Capabilities
PGY-PMBus-EX-PD supports Auto, simple, and advanced trigger capabilities. The analyzer can trigger on any of the PMBus Protocol packets. Advanced Trigger provides the flexibility to monitor Multiple trigger conditions and can set multiple state trigger machines.
PGY-PMBus-EX-PD Specifications
