PCIe Protocol Analyzer

The PGY-PCIeGen3/4-PA is a PCIe Protocol Analyzer that supports protocol analysis up to PCIe Gen4 speeds. PCIe design and test engineers can easily capture and record traces at 2.5, 5.0, 8 and 16GT/s at a specific event and obtain error reports instantaneously at an affordable price. This enables the design and test engineers to reduce the development time and address the time-to-market needs. PCIe Gen4 data is captured using interposers between the root complex and endpoint (Device under test). PCIe Gen4 interposers support. PCIe Gen4 Protocol Analyzer’s software provides complete decode and error analysis of Transaction Layer Packets (TLPs), data link Layer Packets and with LTSSM information.

PCIe Protocol Analyzer

PGY-PCIeGen3/4-PA software provides powerful protocol decode capabilities enabling engineers to quickly identify the problems in the protocol layer. Software is capable of decoding the packets and providing error analysis. Different views of the Protocol layer enables the user to quickly identify the problems in the protocol. Power search, filter-in, filter-out features simplify debug activity.

PGY-PCIeGen3/4-PA provides sophisticated protocol trigger features which allows trigger on specific protocol event and capturing the data of interest. Auto, simple and advanced trigger features capture PCIe bus activity, specific events and monitor multiple trigger conditions and capture data around it.

Key Features

  • PCIe Gen1/2/3/4-X4 Protocol Decode and Analysis.
  • Currently supports four lane PCIeGen1/2/3/4 Bus.
  • Active M.2 Connector interposer for speeds up to PCIe Gen4 is standard offering with protocol analyzer.
  • Optional Passive M.2 Connector interposer for speeds up to PCIe Gen3.
  • Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
  • Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
  • Hardware based protocol packet TS1, TS2 and IDLE filter capabilities.
  • Software based search, filter-in and filter-out capabilities.
  • Hardware based protocol aware trigger capabilities.
  • Advanced multi-level if-then-else if trigger capabilities.
  • Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
  • Trigger based on TS1, TS2, TLP and DLLP Packet content.
  • Detailed view of each TLP/DLLP with all field values.
  • LTSSM Analysis for PCIe protocol traffic.
  • Memory segmentation with each segment with different trigger condition¹.
  • Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
  • Interface to host system using USB 3.0.
  • Decoded data packets can be exported to .txt file for further analysis.
  • PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
  • Field upgradeable enables the unit to easy maintain for latest feature set.
1. Will be supported in our future release

PCIe Specifications


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