PCIe Gen 3 Protocol Analyzer Datasheet

The PCIe Gen 3 Protocol Analyzer (PGY-PCIeGen3-PA) is a PCIe Protocol Analyzer that supports protocol decode and analysis of PCIe Gen1/2/3-X 16. PCIe design and test engineers can easily captures and record traces at 2.5, 5.0 and 8 GT/s at specific event and obtain error report instantaneously at affordable price. This enables the design and test engineers to reduce the development time and address the time to market needs. PCIe Gen3 data is captured using interposers between the root complex and end point (Device under test). PCIe Gen3 interposers support. PCIe Gen3 Protocol Analyzer’s software provides complete decode and error analysis of Transaction Layer Packets (TLPs), data link Layer Packets and with LTSSM information.

PCIe Gen 3 Protocol Analyzer Datasheet

Key features

  • PCIe Gen1/2/3-X 16 Protocol Decode and Analysis
  • Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
  • Hardware based protocol packet TS1, TS2 and IDLE filter capabilities
  • Software based search, filter-in and filter-out capabilities.
  • Hardware based protocol aware trigger capabilities
  • Advanced multi-level if-then-else if trigger capabilities
  • Standard buffer size of 16GB for TX and RX.
  • Trigger based on TS1, TS2, TLP and DLLP Packet content.
  • Detailed view of each TLP/DLLP with all field values
  • LTSSM Analysis for PCIe protocol traffic
  • Memory segmentation with each segment with different trigger condition1.
  • Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
  • Interface to host system using USB 3.0.
  • Decoded data packets can be exported to .txt file for further analysis.
  • PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
  • Field upgradeable enables the unit to easy maintain for latest feature set.
  • 1. Will be supported in our future release

PGY-PCIeGen3-PA software provides powerful protocol decode capabilities enabling engineers to quickly identify the problems in protocol layer. Software is capable of decoding the packets and provide error analysis. Different views of Protocol layer enables the user to quickly identify the problems in protocol. Power search, filter-in, filter-out features simplify debug activity.

PGY-PCIeGen3-PA provides sophisticated protocol trigger features which allows trigger on specific protocol event and capturing the data of interest. Auto, simple and advanced trigger features capture PCIe bus activity, specific event and monitor multiple trigger conditions and capture data around it.

Specifications

Pcie Version Supported PCIe Gen1, Gen2, Gen 3,
Data Rate Supported  2.5, 5.0 and 8 GT/s
Link Width x1, x2, x4, x8 and x16
Buffer Size 16 GB Tx, 16 GB Rx
Probes  PCIe Gen 3.0 CEM Interposer Qty 1
Protocol Decode TS1, TS2, TLP, DLLP, SDS, IDLE, EIOS, EIEOS, FTS, SKP, Memory, IO, message, and configuration space
Trace Capture Size Supports Continuous streaming of Protocol data to Host computer SSD/HDD. And Post Capture up to buffer size.
Trigger Based on TS1, TS2, TLP, DLLP.
Connectors Interface for Active probes. Trigger in/out SMA connectors.
Interface for Host Computer USB 3.0.
Host Computer Requirements Processor: Intel i7 10th Generation or better (Equivalent)

Operating System: Windows 7/8.0/8.1/10 64bit OS.

RAM:  minimum 16GB but the product would give a faster response for 32GB/64GB/more.

Storage: 256GB SSD or more (minimum storage capacity of 1GB should be available in the hard disk drive. User can use more storage based on trace storage requirement.)

Display resolution: 1024X768.

Interface: Host computer should support USB 3.0 interface.

Power Requirement 12V, 6A DC Power Supply (AC/DC Supplied along with Analyzer).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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